FPGA Design Engineer @ MISTRAL SOLUTIONS

Skills: FPGA RTL design, Place and Route and Timing closure have participated in design, implementation and on-board testing of FPGA. Should have worked in IS0 9001 2000 or CMMi level 3 processes Languages : Working knowledge of VHDL, Verilog for RTL synthesis Tools : Shall have worked on Altera Quartus, Symplify, Precision RTL or Xilinx ISE Modelsim or NC-Verilog, NC-VHDL Experience: 1-3 years Location: Bangalore